Wafer-level chip-scale packaging (WLCSP) is attractive because it allows engineers to implement a very small package profile while minimizing interconnect lengths. Today’s WLCSPs are generally an afterthought in the design process. Engineers usually analyze and consider the effects only after completing the IC design. As complex 5G and automotive phased array systems move to higher mmWave frequencies (60 GHz), packaging effects begin to dominate performance, meaning the package design needs to become an integral part of the IC development process. This webinar will illustrate an approach to analyzing WLCSPs in real time as part of the design process.
What you will learn:
This is part of our Keysight Engineering Education Webinar Series