With the ink barely dry on the PCI Express (PCIe) 5.0 specification, PCI-SIG launched headfirst into its next-generation technology, announcing the PCI Express 6.0 specification in June 2019. This iteration is slated to deliver a blistering 256 gigabytes per second (GB/s) of data across 16 lanes. That is double the speed of PCIe 5.0-based technology. It is four times as fast as PCIe 4.0 devices that have only recently become available in the marketplace. PCI-SIG aims to achieve this performance bump by using four-level pulse amplitude modulation (PAM4) technology. It will carry twice as much data over similar channels and frequencies as non-return-to-zero-based technologies such as those used in PCIe 5.0 devices.
In this webinar, you will learn the latest information on the PCIe 5.0 standard. The webinar will discuss key techniques to help you perform transmitter (Tx) and receiver (Rx) characterization and debug of PCIe 5.0 devices operating at 32 gigatransfers per second (GT/s). Learn about considerations for PAM4-based signaling from a transmitter validation and receiver testing perspective. Since many of you are working on PCIe 3 and PCIe 4 technology, this webinar will touch on how the next generation leverages tools and techniques for measurement and validation developed for these earlier iterations of the standard. The good news is that all generations of PCIe feature backward compatibility. Therefore, it is important to understand how to validate all speeds of PCIe technology, regardless of what you decide to use as your top speed gear.
This is part of our Keysight Engineering Education Webinar Series