JEDEC has not yet released the DDR5 specification, and the details remain confidential. However, doubling DDR4’s already high speeds requires memory system designers to have an unprecedented understanding of important advanced techniques.
In this webinar, design and test engineers will learn about the latest updates on DDR5 technology development. They will also learn new design and measurement techniques for this next-generation memory channel and for transmitter, receiver, and protocol test. The webinar will review the trends and technologies influencing thinking on DDR6, which may look very different from DDR5.
This is part of our Keysight Engineering Education Webinar Series