Massive data flow from 5G, artificial intelligence (AI), virtual reality (VR), Internet of Things (IoT), and autonomous vehicles are creating unprecedented demand for bandwidth everywhere in the network and data center.
High-speed digital standards are evolving quickly to support high-performance computing and communication.
Learn the latest trends and solutions for data center networking and computing (PCIe® 5.0, DDR5) as well as the telecom network for 400G and beyond.
PCIe® is a US registered trademark and/or service mark of PCI-SIG.
9:00 a.m. Keynote: Data Center and Optical Network Innovation: Enabling the 5G Ecosystem
Speaker: Brig Asay, Director, Strategic Planning, Internet Infrastructure Group, Communications Measurement Solutions, Keysight Technologies
5G mobile communications will give rise to opportunities for a higher quality of service (QoS) and bandwidth, as well as low latency applications and services. This trend is driving the need for a new higher performance computing and wireline network infrastructure. Research, development, and manufacturing must be completed on a tight timeline and within a competitive cost envelope — without compromising quality. This keynote offers new insight into the state of the industry and highlights future trends for high-speed computing, 400G/800G data center networking, terabit metro/long-distance networks, and the 5G wireline fronthaul infrastructure.
9:30 a.m. Reduce Simulation Complexity and Get Ready for DDR5
Speaker: Aik Chun Ng, Technical Consultant, EEsof Electronic Design Automation, Keysight Technologies
DDR memory designs grow more complex with each new generation, and simulation and test configuration also grow in complexity, resulting in longer simulation and test setup times. The added complexity makes it harder to correlate simulation and test data, resulting in less confidence in designs, longer troubleshooting cycles, and missed delivery schedules. The new PathWave ADS Memory Designer makes it easy for developers to compare simulated data with actual measured results, reducing the time required to complete product development workflows. It connects simulation and test workflows, addressing common DDR memory design challenges with new workflows that automate routine tasks and harness data analytics to gain faster actionable insight into simulation data.
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