Divide and Conquer: Hierarchical DFT for SoC Designs
May 27, 2014 === === Large System on Chip (SoC) designs present many challenges to all design disciplines, including design-for-test (DFT). By taking a divide-and-conquer approach to test, significant savings in tool runtime and memory consumption can be realized. This whitepaper describes the basic components of a hierarchical DFT methodology, the benefits that it provides, and the tool automation that is available through Mentor’s Tessent tool suite.

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