Improve Logic Test with a Hybrid ATPG/BIST Solution
January 10, 2014 === === Two test strategies are used to test virtually all IC logic—automatic test pattern generation (ATPG) with test pattern compression, and logic built-in self-test (BIST). For many years, there was a passionate debate between some DFT practitioners about which is the best test method— ATPG or BIST. ATPG has been dominant for years, and is now used for full-chip test across the electronics industry. However, the use of logic BIST has increased lately with the higher demand to be able to test chips in a system or with limited tester interface, such as for burn-in test, board test, and MCM (multi-chip module).
Recently, the differences between the two test approaches have slightly blurred, and now DFT implementations can efficiently share logic between the two approaches. Thus, for some designs, the decision isn’t between using ATPG or logic BIST but to how to use them together. This paper will describe how ATPG and logic BIST work, explain the differences between them, and offer guidelines on when to use one, the other, or a mixture of both.