Improve Reliability with Accurate Voltage-Aware DRC
September 12, 2013 === === Power challenges in today's IC designs create a significant increase in verification complexity. Critical design rule checking of variable spacing rules for densely packed multi-voltage nets is often verified with the traditional use of marker layers, a tedious and error-prone technique. Without an efficient means of verifying variable spacing within nets, designers often play it safe and simply apply maximum spacing throughout specific areas of a design, wasting valuable design area. Learn how to: • Optimize design size with correct voltage spacing rules • Avoid TDDB within your designs • Improve reliability and free yourself from manual marker layers

If you have previously registered for any IEEE Spectrum webinar or whitepaper, please login below:

Email *
Password *  Forgot Password?
  

Email *
Password *
First Name *
Last Name *
Job Title *
Company *
Industry *
Street Address Line 1 *
Street Address Line 2
City
State/Province *
Zip/Postal Code *
Country *
Work Phone *
Are you an IEEE Member? *
 I would like to receive information from IEEE Spectrum Online on the latest webcasts, news, and technology advances.
* Designates a required field