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Nvidia Presents: Comprehensive Layout-based ESD Check Methodology with Fast, Full-chip Static and Macro-level Dynamic Solutions
Event Date: Wednesday, October 02, 2013 at 10:00 AM PDT This presentation will discuss a comprehensive ESD static/dynamic methodology developed for pre-tapeout ESD verification, failure diagnosis, and predictive simulation of improvements. The methodology focuses on fast, full-chip static and macro-level dynamic analysis and will feature real HBM and CDM application examples. We will also discuss the potential impact of upcoming technologies on ESD including 3D-ICs, FinFETs, and system-level trade-offs. Main products covered: PathFinder

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