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SoC Designers, Get a Clear Vision of 20-nm Success

Date: August 09, 2011
Time: 11AM PT / 2 PM ET
Duration: 45 minutes + Q&A

With lithography limits, double patterning, high-k gates, low-k interconnects and myriad new requirements, the path to silicon success at the 20-nm node can look a little fuzzy. You need an advanced, scalable, integrated SoC design environment that delivers fast and predictable timing and layout closure. Attend this webcast to get a clear vision of how Magma’s Silicon One technology can get your 20-nm SoC to silicon fast and with better results.

What you will learn:

• How tight integration of all analog and digital tools delivers an optimal 20-nm SoC flow.
• Why deploying a fully sign-off-ready flow is easier than you think.
• What you can do to address DFM issues such as double patterning rules while maintaining high routing and placement density.


Mark Richards
Senior Technical Marketing Manager,
Digital Implementation Business Unit,
Magma Design Automation

Mark Richards has a strong background in RTL-to-GDSII implementation. As a product engineer at Magma he has worked through the full spectrum of the implementation flow and now brings that technical expertise to his marketing role. He was instrumental in incorporating critical 28-nm design capabilities into Magma’s Talus platform, worked closely with TSMC, GLOBALFOUNDRIES and other partners to ensure Talus support for their 28-nm process technologies and aligned many key customers to the Talus flow for current and future production work. Prior to joining Magma, Mark Richards held Senior Engineering roles at LSI Logic Europe Ltd., nSine and 3Dlabs (now ZiiLabs). Mark Richards is a member of the United Kingdom’s IET and holds a combined Bachelors and Masters of Engineering Degree from the University of Birmingham, England.