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Faster Bug-Free Clock Gating Verification with VC Formal



Web event: Faster Bug-Free Clock Gating Verification with VC Formal
Date: July 11, 2017
Time: 10:00 AM PDT
Duration: 60 minutes

In today’s world, power efficient devices are a necessity and no longer a “nice to have”. Designers are driven to reduce power consumption for their designs using many techniques, including effective insertion of clock gating logic. With the introduction of clock gating cells and corresponding logic, it is required to compare the RTL models before and after power optimization. Traditionally, rerunning the entire simulation tests were necessary, but this approach is time consuming and non-exhaustive. Formal Logic Equivalence Checking (LEC), initially appears to be a good fit but these solutions cannot verify sequential modifications.

In this webinar, we discuss clock gating optimization, its verification challenges and how to achieve faster bug-free clock gating verification with Synopsys’ VC Formal™ Sequential Equivalence Checks (SEQ) application. We will demonstrate VC Formal’s unique capabilities to identify clock gating bugs and how to quickly resolve using Synopsys’ Verdi debug solution. We will also highlight advanced features that address the closure of bounded coverage analysis.


Speakers:

Kiran Vittal
Product Marketing Director, Verification Group

Kiran Vittal is a product marketing director at Synopsys, with 25 years of experience in EDA and semiconductor design. Prior to joining Synopsys, Kiran held product marketing, field applications and engineering positions at Atrenta, ViewLogic, and Mentor Graphics. He holds a MBA from Santa Clara University and a Bachelors in Electronics Engineering from India.


Neelabja Dutta
Senior Corporate Applications Engineer, Verification Group

Neelabja Dutta is a senior corporate applications engineer at Synopsys, who currently specializes in VC Formal and formal verification methodology. He has over 5 years of work experience in formal verification applications, property verification and transaction based equivalence. His background also includes assertion based verification and VCS coverage, and has a total of 11 years of work experience in the EDA industry.



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