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Accurate Power Analysis Earlier & Faster – Using Synopsys PowerReplay and Synopsys PrimeTime PX



Web event: Accurate Power Analysis Earlier & Faster – Using Synopsys PowerReplay and Synopsys PrimeTime PX
Date: June 01, 2017
Time:10:00 AM PDT
Duration: Simulation

Today’s SoC teams are required to meet demanding power targets. Traditionally, accurate power analysis happens too late in the flow for making design changes if power targets are missed. Consequently, designs are either taped out late or without meeting power specifications. Both situations are undesirable and can incur significant costs for companies, not to mention missed time-to-market windows. Hence, there is a pressing need for power analysis that is accurate enough to base design changes on, yet early enough in the flow to accommodate those design changes.

Synopsys PowerReplay is a new solution for early and fast gate-level power analysis with PrimeTime PX. It is available starting from the 17.03 release.

In this webinar, we will cover:
  • How Synopsys PowerReplay and PrimeTime PX enable SoC designers to make timely design optimizations to achieve power targets
  • How PowerReplay applies RTL simulation data on gate-level netlist runs for power analysis accurate within 5% of power signoff
  • How to avoid running exhaustive gate-level simulations by targeting power analysis on specific areas of the design during key power consumption windows

Speakers:

Vaishnav Gorur
Product Marketing Manager, Verification Group, Synopsys

Vaishnav Gorur is currently Staff Product Marketing Manager in the Verification Group at Synopsys. He has more than 12 years of experience in the semiconductor and EDA industry, with roles spanning logic design, field applications, technical sales and marketing. Prior to joining Synopsys, Vaishnav worked at Silicon Graphics, MIPS Technologies and Real Intent. He has a Masters degree in Computer Engineering from University of Wisconsin, Madison and is currently pursuing an M.B.A. at University of California, Berkeley.


Chun Chan
Director, Corporate Applications Engineering, Verification Group, Synopsys

Chun Chan is currently CAE Director in the Verification Group at Synopsys. He has over 20 years of experience in the semiconductor and EDA industry, with roles in verification product development, physical design products, chip package software, ASIC design flow. Prior to joining Synopsys, Chun worked at LSI Logic and led a CAD development team of clock, power, delay, and package software. He was granted 5 patents at LSI Logic. Chun has a Master’s degree in Electrical and Computer Engineering from The University of Texas at Austin.

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