Faster SoC Connectivity Verification with VC Formal

Web event: Faster SoC Connectivity Verification with VC Formal
Date: March 08, 2017
Time:10:00 AM PST
Duration: 60 minutes

As SoCs grow in size and complexity, so does the effort and time required to verify them. Formal verification provides a powerful and complementary way of validating certain complex verification problems. One such category of problems is SoC connectivity applications. This includes verification challenges including correctly sharing pins across blocks of the SoC, properly stitching multi-mode/configurable IP blocks together, and ensuring global SoC signals are properly connected to their low-level counterparts. With multi operation modes, tens of thousands of configurable connections and SoCs spanning hundreds of millions of gates, the correctness of the connections becomes increasingly difficult and time consuming to verify.

This webinar showcases the benefits of using VC Formal’s Connectivity Checking App to validate a wide range of connectivity verification applications. We will show several use-cases where there has been a successful deployment of formal connectivity checking for faster and more thorough validation. These use-cases will help new users identify the complex verification problems that can benefit from using formal connectivity checking. Through examples and demos the benefits of VC Formal’s Connectivity Checking App, such as faster verification closure, exhausting/complete verification, push-button and reusable flow, and no requirement of formal verification expertise will be demonstrated.


Anders Nordstrom
Sr. Corporate Applications Engineer, Synopsys Verification Group

Anders is a senior corporate applications engineer in Synopsys’ Verification Group working on formal methodology and features on the VC Formal tool. He has 20 years’ experience of assertion based verification and formal property verification both from EDA and as a verification engineer.

Sean Safarpour, Ph.D
Formal Verification CAE Manager, Synopsys

Sean Safarpour is a CAE Manager for Synopsys’ Formal Verification products and is currently on the technical programs committees for FMCAD and DVCon. He has over 15 years of experience in the semiconductor industry and was previously Sr. Technology Director at Atrenta and Founder/CTO at Vennsa Technologies. He has also performed similar roles at Altera, Infineon and Intel. Sean has a Ph.D. and M.A. Sc. in Computer Engineering from the University of Toronto.

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