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Accelerated Power Analysis and Verification with Synopsys Verdi Technologies



Date: November 08, 2016
Time:10:00 AM PST
Duration: 30 minutes

From high end servers to consumer electronics to wearables, today’s devices are designed to operate within a specific power envelope. SoC teams utilize sophisticated low power design techniques and implement complicated power management architectures in order to meet power targets. However, low power verification typically happens late in the traditional design flow, and subject to tight deadlines, some low power design features often get scaled back due to incomplete verification. As a result, chips become less feature-rich than intended, potentially losing their competitive advantage.

In this Synopsys webinar, discover how native integrations of Verdi design debug technologies with Synopsys’ power analysis and verification solutions help catch power-related bugs earlier and faster. The industry-leading Verdi platform couples powerful tracing techniques with unique source code and schematic browsers, enabling teams to quickly debug low power issues in RTL or netlist designs, as well as in the UPF power intent specification. These specialized power-aware debug capabilities accelerate low power verification and ensure successful delivery of intended low power features.


Speakers:
Vaishnav Gorur
Product Marketing Manager, Verification Group


Vaishnav Gorur is currently Staff Product Marketing Manager for debug products in the Verification Group at Synopsys. He has more than a decade of experience in the semiconductor and EDA industry, with roles spanning IC Design, field applications, technical sales and marketing. Prior to joining Synopsys, Vaishnav worked at Silicon Graphics, MIPS Technologies and Real Intent. He has a Masters degree in Computer Engineering from University of Wisconsin, Madison and is currently pursuing an M.B.A. at University of California, Berkeley.


Ankush Bagotra, Staff Engineer, Verification Group

Ankush Bagotra is a staff engineer in the verification group at Synopsys. Ankush joined Synopsys in 2008 and is responsible for Low Power and Power Estimation Technologies. Ankush has over 13 years of experience in Semiconductor Design and EDA industries. Prior to joining Synopsys, he was with Atrenta working on Physical technologies. Ankush has a Bachelor’s degree in engineering from BITS Pilani.



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