Catch low-power simulation bugs earlier and faster with Verdi Power-Aware Debug

Synopsys Power Verification & Analysis Webinar Series – 4 part series
Web event: Catch low-power simulation bugs earlier and faster with Verdi Power-Aware Debug
Date: August 31, 2016
Time:10:00 AM PDT

Duration: Debug

Each new generation of consumer electronics devices is expected to have longer battery life than the previous one. Even high end servers compete on low power consumption and cooling costs. This power reduction is made possible by a sophisticated power architecture whose verification, especially debug, poses a significant challenge given the disjoint nature of the implementation - design specification written in RTL and power architecture specified via UPF.
In this webinar, we will demonstrate how Verdi Power-Aware Debug greatly simplifies low-power debug and identifies potential design-killing bugs earlier and faster, with a unified and comprehensive view of the design and its power intent. Specifically, you will learn:
  1. How visualization of the power architecture can help identify power strategy and connectivity issues upfront
  2. How to use annotated power intent on source code, schematics and waveforms to rapidly root-cause power-related errors back to UPF/RTL
  3. How to debug unexpected design behavior such as Xs caused by incorrect power-up/down sequences etc.


Vaishnav Gorur
Product Marketing Manager, Verification Group

Vaishnav Gorur is currently Staff Product Marketing Manager for debug products in the Verification Group at Synopsys. He has more than a decade of experience in the semiconductor and EDA industry, with roles spanning IC Design, field applications, technical sales and marketing. Prior to joining Synopsys, Vaishnav worked at Silicon Graphics, MIPS Technologies and Real Intent. He has a Masters degree in Computer Engineering from University of Wisconsin, Madison and is currently pursuing an M.B.A. at University of California, Berkeley.

Archie Feng
Corporate Applications Engineer, Verification Group

Archie Feng is currently a Corporate Applications Engineer for debug products in the Verification Group at Synopsys. He has more than 15 years of experience in IC design and the EDA industry. Prior to joining Synopsys, Archie was an ASIC designer at the Industrial Technology Research Institute of Taiwan and has held positions in software design, applications engineering and product marketing at Springsoft. He has a Bachelors in Engineering Science from National Cheng-Kung University and a Masters in Computer Science from National Chung-Cheng University in Taiwan.

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