Restrictive Design Rules and Their Impact on 22 nm Design and Physical Verification
November 4, 2009 === === Process variability is posing considerable challenge to the capability of lithography and manufacturing techniques, and thus impacts both performance and yield of advanced node chips. To ensure the manufacturability and performance of chips at 22 nm, one approach the industry is considering is restrictive design—limiting the type and placement of features used in designs. Gridding of critical layers significantly reduces the total physical design space available and makes restrictive design possible. This paper will examine the basics of gridding, the requirements for restrictive gridded design, and the automated methods for accurate checking of Restrictive Design Rules (RDRs). Resolving the debug challenges associated with the implementation of checking restrictive design and grid rules will also be discussed.

If you have previously registered for any IEEE Spectrum webinar or whitepaper, please login below:

Email *
Password *  Forgot Password?

Email *
Password *
First Name *
Last Name *
Job Title *
Company *
Industry *
Street Address Line 1 *
Street Address Line 2
State/Province *
Zip/Postal Code *
Country *
Work Phone *
Are you an IEEE Member? *
 I would like to receive information from IEEE Spectrum Online on the latest webcasts, news, and technology advances.
* Designates a required field