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Reduce Power Consumption 30% with Advanced Synthesis Techniques
 This presentation will be available to audience members until September 24, 2014 at 12:00 PM Pacific Daylight Time.
 
  Web event: Reduce Power Consumption 30% with Advanced Synthesis Techniques
Date: April 14, 2011
Time:10:00 AM PDT
Duration: 1 hour


In this webinar you will learn how new advances in clock gating and voltage threshold (Vt) optimization available in Design Compiler can reduce your dynamic and leakage power by 10-30%. You will also have the opportunity to engage in an interactive Q&A session following the technical presentation.




Speakers:

Mary Ann White
, Product Marketing Director, Synopsys

Rishi Chawla, Sr. Application Engineering Manager, Synopsys
 
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