Best Practices to Accelerate GPU Prototyping with HAPS
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  Web event: Best Practices to Accelerate GPU Prototyping with HAPS
Date: July 18, 2017
Time: 10:00 AM PDT
Duration: CoreEDA/Galaxy

This webinar outlines best practices for prototyping Graphic Processing Units (GPU) with HAPS. Besides the traditional consumer applications, GPUs are playing an increasingly important role in emerging areas such as artificial intelligence. Software standards in these domains are quickly evolving and impose increasing requirements on the underlying hardware architecture. Pre-silicon software development and validation using FPGA-based prototypes has become the norm to mitigate the risk of design defects or late software. A large portion of software development can be performed using a basic GPU prototype with a limited number of shader cores performing at a high operating frequency on a single FPGA. Advanced software and validation use cases demand full GPU prototypes with tens of shader cores. Even more complex are gaming class GPU prototypes, which are highly complex and may span several FPGAs.

This webinar provides guidance on how to approach and plan a GPU prototyping project in terms of hardware requirements, resources, and timeline. We will outline the various bring-up and prototype validation phases and explain how to approach design preparation and partitioning of the GPU design. Best practices for the hardware setup, which comprises connecting and synchronizing many HAPS systems will also be shared.


Paul Owens
Sr. Technical Marketing Manager, Synopsys

Paul Owens is a senior Technical Marketing Manager within the Synplify Business Group at Synopsys. Paul has worked in Design Automation, CAE, ASIC and FPGA design and verification. He holds a BS in Electrical Engineering from U.C. Berkeley, and an MS in Computer Engineering from Santa Clara University.

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