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Using High-Level Synthesis for the Design and Optimization of Multi-Rate Communications Hardware
  This event was broadcast on May 25, 2011 and will be available on demand until November 25, 2012.
  Web event: Using High-Level Synthesis for the Design and Optimization of Multi-Rate Communications Hardware
Date: May 25, 2011
Time:9:00 AM PDT


Duration: 1 hour

Many communications systems use multiple sample rates in their signal processing paths. It can be challenging to efficiently implement these algorithms in ASIC or FPGAs because of the complexity in supporting multiple clock domains and because of the many architectural tradeoffs between area, speed, and power that can exploit the multiple sample rates in the design. This webinar shows how high-level synthesis optimizations can be used to more easily create efficient hardware architectures and also explore tradeoffs while keeping the multi-rate algorithm development simple. Wireless communications designs for FPGA and ASIC will be used to illustrate the concepts.

What you will learn:
  • How to efficiently implement multi-rate communication algorithms in both ASIC or FPGA
  • Common architecture optimizations and tradeoffs in multi-rate hardware architectures
  • Design and verification flows for high-level synthesis and model-based design


Who should attend:
  • Algorithm developers of signal processing hardware
  • System engineers and architects of wireless, mil/aero, telecom, and industrial applications
  • Hardware and verification engineers of FPGA and ASIC hardware

Presenter:

Chris Eddington
Product Marketing Director
High-Level Synthesis
Synopsys, Inc.

Chris Eddington is the Product Marketing Director for High-Level Synthesis products at Synopsys. Chris has 20 years of experience in ASIC and FPGA design for communications and multimedia products. His previous role was Technical Marketing Director for high-speed networking ICs at Mellanox Technologies and prior to that he held various positions as Lead IC Designer for VOIP processors, video conferencing ICs, and wireless communications systems. He holds an MS engineering degree from the University of Southern California and an undergraduate degree in Physics and Math from Principia College.
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